1. Field of the Invention
This invention relates to a data-driven processor, and more particularly to a data-driven processor which can easily process packets including only untagged data without the so-called tag information, such as the module number and the destination address, and output the packet only of a data field in a predetermined order.
2. Description of the Prior Art
The data-driven processor is also called the data flow processor and is a computer which basically executes a data-driven principle that "whenever pairs of data required for processing are complete, the processing may be executed".
Conventionally, this kind of information processor has been cited on the thesis of a Data Flow Processor Aiming at the Image Processing Field (Matsumoto et al., Nikkei Electronics No. 340, pp. 181-218, Apr. 9, 1984). Next, explanation is given on the conventional example on the basis of the thesis:
FIG. 1 is a block diagram of the above-mentioned data-driven microprocessor, in which a reference numeral 1 designates an input control unit, 8 designates an output control unit, 2 designates a link table unit, 3 designates a function table unit, 4 designates a matching memory unit, 5 designates a queuing unit, 6 designates an operation unit, and 7 designates an output queuing unit.
FIG. 2 shows change in form of the packets and the content of each table used in the processor shown in FIG. 1. In FIGS. 2-(a) through (e), reference numerals 9 through 13 designate packets respectively. At the packet 9, a reference numeral 101 designates module number MN, 102 designates a destination addresses (ID), and 103 designates data. At the packet 11, a reference numeral 112 designates the next destination address (ID'), 105 designates a function table address (FTA), and 106 designates a selection code (SEL). At the packet 12, a reference numeral 107 designates the matching memory address (MMA), and 108 designates an operational code (OPC). At the packet 13, reference numerals 131 and 132 designate first and second data respectively.
In FIGS. 2-(f) through (h), reference numerals 14 to 16 designate a link table (LT), a function table (FT) and a matching memory (MM) respectively, and 0 to 127, 0 to 63 and 0 to 511 designate their own addresses respectively. At the link table 14, a reference numeral 205 designates a function table address, 212 designates the next destination address, and 206 designates a selection code. At the function table 15, a reference numeral 207 designates a matching memory address, and 208 designates an operational code. At the matching memory 16, a reference numeral 230 designates data.
Next an explanation of the operation of the conventional data-driven processor follows:
The packet 9 shown in FIG. 2-(a) is introduced into the information processor constructed as shown in FIG. 1. The module number (MN) 101 at the packet 9 having reached the input control unit 1 is compared with a module number previously given to the information processor, so that, when not coincident, the packet is sent as it is to the output control unit 8 and outputted to the exterior. Otherwise, packet 10 except for the module number (MN) 101 (see FIG. 2-(b)) is sent to the link table 2 only when coincident.
The link table unit 2 uses the destination address (ID) 102 at the packet 10 as the address and its link table 14 is referred. As a result, and the function table address (FTA) 205 for reading out the function table (FT) 15, the next destination address (ID') 212 for reading out the link table 14 when the packet 10 reaches the link table unit 2, and the selection code (SEL) 206 representing sorting of instruction to be given to the packets, are read out and added to the packet 10, thereby forming a new packet 11 (see FIG. 2-(c)) and outputting it to the function table unit 3.
The function table unit 3 uses the function table address (FTA) 105 as the address and refers to its function table (FT) 15, thereby obtaining the parameter group which determines the processing content at the following pipeline stage. A part of the obtained parameters is added directly to the packet 11 as it is and other parts are reprocessed at a control unit (not shown) so that the result is added to the packet 11 so as to form a new packet 12 and then sent to the matching memory unit 4.
For example, the packet 11 received by the function table unit 3 is the packet serving as one operand of a 2-operand operation, and, when the packet serving as the other operand is assumed to have already reached and wait at the matching memory unit 4, the packet 11 at the function table 3 obtains the operational code (OPC) 208 representing the sort of operation and the memory address (MMA) 207 of the matching memory (MM) 16 storing therein other operands of the 2-operand operation and adds them to the packet 11, thereby forming the packet 12 (see FIG. 2(d)).
The matching memory unit 4 reads out the data corresponding to other operands necessary to execute operation and transmits the data as the packet 13 (see FIG. 2-(e)) provided with 2-operands 131 and 132 to the queuing unit 5.
The queuing unit 5 comprises a first-in first-out memory so that, when the packet 13 reaches the head of first-in and first-out memory, it is outputted to the operation unit 6 and operation processing is executed. The packet 10 from the operation result is of a format shown in FIGS. 2-(6b) and to be outputted to the link table unit 2.
Thus, the input packet circulates several times through a pipe line ring 50 comprising the link table unit 2, function table unit 3, matching memory unit 4, queuing unit 5 and operation unit 6, thereby being subjected to required processing. Thereafter, the packet is sent to the function table 3 through the link table unit 2 for the re-outputting, receives an instruction for the output, is sent to the output queuing unit 7 via the matching memory unit 4 and queuing unit 5, and is outputted to the exterior through the output control unit 8.
However, in the processing method described at the conventional example, it is required that the data packet to be processed, when introduced from the exterior, includes the so-called tag information, such as the module number and the destination address, along with data. Also, the data of the processing result is outputted with such tag information being added. Moreover, since a data-driven type computer does not assure the desired order of executing instructions, the data is not always output in the desired order.
Therefore, the problems occur in that
(1) in comparision with the input of data only, the number of pins required input/output of a packet including data and tag information increases, or, if one packet should be divided into a plurality of words for, where the number of words in each output packet is L the input/output rate lowers,
(2) an external device or a host processor is required to add the destination address or the like to the data so as to build up the input packet, and
(3) since the output order of output packets is not generally predetermined, the external device or the host processor is required which decides the destination address of the output packet and rearranges the output packet stream in the predetermined order.